1. Field of the Invention
The present invention relates to an I/O circuit of a semiconductor integrated circuit device whose I/O circuit is employed as an input circuit for inputting to an internal circuit of the semiconductor integrated circuit device, a signal input from an external circuit thereof, or as an output circuit forouteputting to the external circuit, a signal output from the internal circuit, and more particularly relates to the I/O circuit that operates effectively when a signal voltage higher than the voltage of an internal power supply of the semiconductor integrated circuit device is input from the external circuit.
2. Description of the Related Art
FIG. 4 shows a circuit diagram of a conventional input circuit. The input circuit of FIG. 4 is provided inside a semiconductor integrated circuit device (an LSI chip), and inputs a signal input from an external circuit to a pad electrode PAD, from a node OUT to an internal circuit of the LSI chip. An internal power supply VDD is 3[V]. The external circuit inputs a low level (xe2x80x9cLxe2x80x9d level) signal of 0[V] or a high level (xe2x80x9cHxe2x80x9d level) signal of 5[V] to a pad electrode PAD, or sets the pad electrode PAD at a high impedance (xe2x80x9cZxe2x80x9d level). Here, the high impedance (xe2x80x9cZxe2x80x9d level) means that the pad electrode PAD (node I/O) is floating with respect to the external circuit, and with respect to all of the circuits connected to the node (I/O).
In the input circuit in FIG. 4, PMOS transistor P11 and NMOS transistor N15 are OFF all the time. These transistors are provided such that the input circuit of FIG. 4 can be converted to be used as an output circuit easily. When the input circuit of FIG. 4 is used as an output circuit, the transistors are ON/OFF in accordance with a signal input from the internal circuit to respective gate electrodes.
Substrates of PMOS transistors P12 to P17 (N-well layers on which the PMOS transistors P12 to P17 are formed) are connected to a node W11 which is floating with respect to the internal power supply VDD. Accordingly, even when a signal voltage of 5[V], higher than the internal power supply VDD, is input to the pad electrode PAD, flowing of leakage current from the pad electrode PAD to the internal power supply VDD through a pn junction is prevented. The pn junction is formed by source or drain, and a substrate, N-well layer, of PMOS. Further, the PMOS transistors P12 and P15 are OFF when a signal voltage of 5[V] higher than the internal power supply VDD is input to the pad electrode PAD, thereby preventing electric current from flowing in reverse from the pad electrode PAD to the internal power supply VDD.
The PMOS transistors P13, P14, NMOS transistors N11 to N13, and an inverter INV11 convert a signal of 5[V], which was input from the external circuit to the pad electrode PAD, to a signal of substantially 3[V] on the basis of a VIH standard of an internal circuit, and inputs the converted signal to the internal circuit. The VIH standard is one determining voltage tolerance of an xe2x80x9cHxe2x80x9d level input signal.
The NMOS transistors N11 and N14 are provided so as to prevent a voltage greater than or equal to the internal power supply VDD from being applied through drain-source, gate-drain, and gate-source, of each of the NMOS transistors N12 and N15 when a signal of 5[V] is input to the pad electrode PAD. Accordingly, the NMOS transistors N11 and N14 can deal even with an LSI chip manufactured through a process in which voltage tolerance is low.
The PMOS transistor P16 is ON when a signal of 5[V] is input to the pad electrode PAD, and sets the node W11, each substrate of the PMOS transistors P12 to P17, at 5[V].
NMOS transistor N16 and PMOS transistor P17 clamp the node I/O at substantially 3[V] when the pad electrode PAD is at the xe2x80x9cZxe2x80x9d level. Further, since the PMOS transistor P17 is ON when the pad electrode PAD is 0[V] (the xe2x80x9cLxe2x80x9d level) or 5[V] (the xe2x80x9cHxe2x80x9d level), electric current flows between the internal power supply VDD and the pad electrode PAD through a source-drain of the PMOS transistor P17.
However, in the above-described conventional circuit, when the pad electrode PAD is at the xe2x80x9cLxe2x80x9d level, a node S14 is at the xe2x80x9cLxe2x80x9d level, and the PMOS transistors P12 and P15 are ON, an electric current route I1 (see FIG. 4) of [VDD]-[source of P17]-[substrate of P17]-[W11]-[drain of P15]-[S13]-[P12]-[PAD] is formed. Accordingly, there has been a problem in that electric current flowing into the pad electrode PAD becomes larger than a predetermined value (the value of current flowing through the source-drain of the PMOS transistor P17), and consumption of electric current thereby increases. Moreover, the PMOS transistor P15 is provided so as to set the node W11 at the same potential as the internal power supply VDD when the circuit of FIG. 4 is used as an output circuit and the PMOS transistor P11 is ON.
When the pad electrode PAD changes from the xe2x80x9cLxe2x80x9d level to the xe2x80x9cZxe2x80x9d level, the potential of the node I/O is increased by the PMOS transistor P17. However, there have been problems, described below. Namely, as the potential of the node I/O nears the potential of the internal power supply VDD, the potential of the node Sll also increases, electric current characteristics of the PMOS transistor P17 thereby deteriorate, and it takes more time until the node I/O reaches the potential of the internal power supply VDD as compared to a case in which a pull-up transistor (in which the gate electrode of the PMOS transistor P17 is fixed at the xe2x80x9cLxe2x80x9d level) having the same dimensions as the PMOS transistor P17 is employed. Further, because increasing dimensions of the PMOS transistor P17 means increasing electric current consumption, it is not preferable.
Since PMOS and NMOS usually have different thresholds, there have been problems in that, according to a combination of thresholds of the PMOS transistor P17 and the NMOS transistor N16, the PMOS transistor P17 may be OFF before the node I/O increases to the potential of the internal power supply VDD (3[V]) so that the node I/O does not reach to the power supply potential. If the node I/O does not reach the power supply potential (3[V]), a drawback is generated in that a margin for the VIH standard of a signal input from a node OUT to the internal circuit is reduced, or the like.
In order to solve such a conventional problem as described above, the present invention is achieved, and it is an object of the present invention to reduce electric current consumption. Further, it is another object of the present invention to set this node at the potential of the internal power supply reliably when a connecting node of an external circuit is at high impedance.
In order to accomplish the above-described objects, in accordance with an aspect of the present invention, there is provided an I/O circuit of a semiconductor integrated circuit device, comprising: a first MOS transistor (P11) whose gate electrode is connected to a first node (IN1) to which a first signal is input from at least one of a first power supply (VDD) and an internal circuit, of the semiconductor integrated circuit device, whose first electrode and substrate are connected to said first power supply, and whose second electrode is connected to a second node (S13); a second MOS transistor (P12) whose first electrode is connected to said second node, whose gate electrode is connected to a third node (S14), whose second electrode is connected to a fourth node (I/O) to which a signal is either input from an external circuit or from which a signal is output to the external circuit, and whose substrate is connected to a fifth node (W11) which is floating with respect to said first power supply; a third MOS transistor (P15) whose first electrode is connected to said second node, whose gate electrode is connected to the third node, and whose second electrode and substrate are connected to the fifth node; a fourth MOS transistor (P17) whose first electrode is connected to the fourth node, whose gate electrode is connected to a sixth node (S11), whose second electrode is connected to the first power supply, and whose substrate is connected to the fifth node; a first control circuit which controls the potential of the sixth node (S11) in accordance with the potential of the fourth node (I/O); and a second control circuit which controls the potential of the third node (S14) in accordance with the potential of the fourth node (I/O), wherein any of a connection of the fourth node (I/O) and the second electrode of the second MOS transistor (P12), a connection of the first electrode of the second MOS transistor (P12) and the first electrode of the third MOS transistor (P15), a connection of the second electrode of the third MOS transistor (P15) and the fifth node (W11) and a connection of the second electrode of the fourth MOS transistor (P17) and the first power supply (VDD) is disconnected.
In accordance with another aspect of the present invention, there is provided an I/O circuit of a semiconductor integrated circuit device according to claim 1, wherein the first control circuit comprises: a sixth MOS transistor (P28) whose gate electrode is connected to the first power supply, whose first electrode is connected to the fourth node, whose second electrode is connected to the sixth node, and whose substrate is connected to the fifth node a seventh MOS transistor (N27) whose gate electrode is connected to the first power supply, whose first electrode is connected to a second power supply (GND), and whose second electrode is connected to a seventh node (S21); and an eighth MOS transistor (N26) whose gate electrode is connected to the first power supply, whose first electrode is connected to the seventh node, and whose second electrode is connected to the sixth node.